wordpress电影站模版,出国游做的好的网站,网站后台密码,怎样做网络推广引流从SRAM中读写一个数据问题——Verilog2009-04-24 14:21从SRAM中读写一个数据问题——Verilog操作SRAM(IS63lv1024)#xff0c;向SRAM写入一个数据#xff1b;并从SRAM中读出数据#xff1b;如果读出的数据与写入的一样#xff0c;说明写读成功#xff0c;LED2闪烁#xf…从SRAM中读写一个数据问题——Verilog 2009-04-24 14:21 从SRAM中读写一个数据问题——Verilog 操作SRAM(IS63lv1024)向SRAM写入一个数据并从SRAM中读出数据如果读出的数据与写入的一样说明写读成功LED2闪烁否则SRAM操作不成功。现在一直没有实验成功请高手指教谢谢HDL语言VERILOGCPLD芯片XC95144XL-10T100ISRAM芯片IS63lv1024晶振40MLED2电路已经可行。以下是程序module OprateSRAM(clk,key,Addr_OUT,_CE_OUT,_OE_OUT,_WE_OUT,LED2_Flash,LED5_Flash,DMX_out1,DATA_INOUT);input clk;input key;output _CE_OUT;output _OE_OUT;output _WE_OUT;output LED2_Flash;output LED5_Flash;output DMX_out1;output[15:0] Addr_OUT;inout[7:0] DATA_INOUT;reg [15:0] Addr_OUT_reg;reg _CE_OUT_reg;reg _OE_OUT_reg;reg _WE_OUT_reg;reg DMX_out1_reg; reg [7:0] DATA_WRITE_BUFFER;wire [7:0] DATA_READ_BUFFER;reg [7:0] DATA_READ_BUFFER2;wire r_en _WE_OUT (~_CE_OUT) (~_OE_OUT); wire w_en (~_WE_OUT) (~_CE_OUT);//reg SRAM_RE_WR_OK;reg LED2_Flash_reg_1Hz_buffer; // buffer,middile reg LED2_Flash_reg; // putout reg [21:0] LED2_Flash_1Hz_count; // countreg LED5_Flash_reg;reg [5:0] state;reg WR_RD_Return;parameter IDLE 6b000_001,READY 6b000_010,WR_DataNew 6b000_100,WR_AddrNew 6b001_000,RD_DataNew 6b010_000,RD_AddrNew 6b100_000, WR 1, RD 0;assign LED2_Flash LED2_Flash_reg;assign LED5_Flash LED5_Flash_reg;assign DMX_out1 DMX_out1_reg;assign _WE_OUT _WE_OUT_reg;assign _CE_OUT _CE_OUT_reg;assign _OE_OUT _OE_OUT_reg;assign DATA_INOUT w_en? DATA_WRITE_BUFFER:8bz; assign DATA_READ_BUFFER r_en? DATA_INOUT:8bz;assign Addr_OUT Addr_OUT_reg;initialbegin state IDLE; WR_RD_Return WR; Addr_OUT_reg 16b0000_0000_0000_0000;end/******************************************************************** description: use to creat 1Hz wave, * LED2 flashing to show the CPLD running*******************************************************************/always (posedge clk)begin if(LED2_Flash_1Hz_count 3999999)begin LED2_Flash_1Hz_count 0; LED2_Flash_reg_1Hz_buffer 1b0;endelsebegin LED2_Flash_1Hz_count LED2_Flash_1Hz_count 22b0001; LED2_Flash_reg_1Hz_buffer 1b1; endend/****************************************************************** LED2 Flashing* thought LED2 to check the operate******************************************************************/always (posedge LED2_Flash_reg_1Hz_buffer)begin if (DATA_READ_BUFFER2 8b0000_0001) begin // if Write and read SROM OK, LED2 will flashing if(LED2_Flash_reg 1) LED2_Flash_reg 1b0;else LED2_Flash_reg 1b1; end else LED2_Flash_reg 1b1;///* if (key 1b0) begin // here ,the key putdown ,LED5 flashing ,test LED5 hardware if(LED5_Flash_reg 1) LED5_Flash_reg 1b0;else LED5_Flash_reg 1b1; end else LED5_Flash_reg 1b1;//*/end/********************************************************************* key , then push the key ,write one time and read one time * SRAM IS63LV1024, to test SRAM operate**********************************************************************/always (posedge clk)begin//使用状态机的读写SRAM程序case(state)IDLE: begin _CE_OUT_reg 1b0; _OE_OUT_reg 1b1; _WE_OUT_reg 1b1; DATA_READ_BUFFER2 DATA_READ_BUFFER; if(WR_RD_Return WR) state WR_AddrNew; else if(WR_RD_Return RD) state RD_AddrNew; else state 0; endREADY: begin Addr_OUT_reg 16b0000_0000_0000_0000; DATA_WRITE_BUFFER 8b0000_0000; state IDLE; endWR_AddrNew: begin //Addr_OUT_reg Addr_OUT_reg 16b1; //DATA_WRITE_BUFFER DATA_WRITE_BUFFER 8b1; Addr_OUT_reg 16b0000_0000_0000_0001; DATA_WRITE_BUFFER 8b0000_0001; state WR_DataNew; endWR_DataNew: begin _CE_OUT_reg 1b0; _WE_OUT_reg 1b0; _OE_OUT_reg 1bz; WR_RD_Return RD; state IDLE; end RD_AddrNew: begin Addr_OUT_reg 16b0000_0000_0000_0001; state RD_DataNew; end RD_DataNew: begin _WE_OUT_reg 1b1; _CE_OUT_reg 1b0; _OE_OUT_reg 1b0; WR_RD_Return 1bz; state IDLE; end endcase endendmodule转载于:https://www.cnblogs.com/FPGA_DSP/archive/2010/02/23/1672192.html
